1) Field of the Invention
The present invention relates generally to fabrication of capacitors in a DRAM cell and particularly to a method for fabricating a three dimensional storage electrode for high reliability and large cell capacitance for memory cells and more particularly a method to form a crown capacitor.
2) Description of the Prior Art
Dynamic random access memories (DRAMs) have a plurality of memory cells, each of which generally includes a storage capacitor and a transistor serving as a transfer gate for storing or eliminating charges. The plurality of memory cells are arranged on a substrate in a matrix arrangement and operate to permit only a single cell in the memory to be selected by means of two dimensional addressing within a given time period. A bit line (data line) voltage is supplied to the storage capacitor via a transistor so as to write information on each memory cell. Also, in order to read out the written information, the storage capacitor is connected to the data line via a gate and the voltage of the storage capacitor is thus monitored.
A serious obstacle to increasing packing density in dynamic random access memories (DRAMs) is the decrease in cell capacitance caused by reduced memory cell area. The problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such capacitor include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors.
Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable to the three-dimensional stacked capacitor, and is more particularly suitable for an integrated memory cell which is 64 Mb or higher. Also, an improve stacked capacitor has recently been presented, where pillars or another inner cylinder is formed in the interior of the cylinder. Not only may both of the inner and outer surfaces of the cylinder be utilized as the effective capacitor area, but also the outer surface of the pillars or the inner cylinder formed in the interior of the cylinder.
The following U.S. patents show related processes and capacitor structures: U.S. Pat. Nos. 5,399,518, Sim et al.; 5,389,568, Yun; 5,389,560, Park; 5,380,673, Yang; 5,372,965, Ryou. Many of the prior art methods require substantially more processing steps or/and planar structures that make the manufacturing process more complex and costly. For example, U.S. Pat. No. 5,399,518 to Sim teaches a method of forming a double-cylindrical storage electrode of a capacitor. The method begins by forming an oxide cylinder on a polysilicon layer. Next, first and second spacers are formed on the sidewalls of the oxide cylinder. The uncovered areas of the polysilicon layer are etched to define electrodes. A second etch is used to etch out an insulation layer beneath the electrode. Next, the oxide spacer and second spacer are removed leaving the first silicon nitride spacer on the electrode top surface. Using the nitride spacer as a mask, top portions of the electrode are removed forming a cylindrical upward stepped portion on the electrode surface. Third spacers are formed on both sides of the upward stepped portion. Using the third spacers as a mask, the electrode is etched forming, under the third spacers, the two crowns of the double cylindrical electrode. However, this method could be improved upon by reducing the number of process steps. This method has the disadvantage of the extra process steps in forming an oxide cylinder and the first and second spacers. Moreover, two etch steps are required just to define the individual electrodes. Overall, the method of Sim could be improved if a method were invented that did not require an oxide cylinder and three sets of spacers to define a double crown and that did not require two etches just to define the individual electrodes.
There is a challenge to develop methods of manufacturing crown capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of process steps and provide maximum process tolerance to maximize product yields.